1. Field of the Invention
The present invention generally relates to an insulator, and more particularly to a lattice-matched epitaxial insulator structure formed on silicon, and arbitrarily grown, lattice-matched epitaxial insulator-silicon and germanium structures grown on top of each other.
2. Description of the Related Art
Prior to the present invention, there has not been any demonstrated lattice-matched epitaxial insulator structure formed on silicon where the lattice constant of the oxide can be varied arbitrarily so that it is equal to, or an integral multiple of the lattice constant of silicon. However, such lattice-matched epitaxial insulator structures on Si are needed for various reasons.
Firstly, such insulators can be used as gate dielectrics for Si complementary metal oxide semiconductor (CMOS) transistors with the view that an epitaxial structure will be less defective. Such epitaxial structures based on SrTiO3-type perovskite structures have been grown as described in “Crystalline Oxides on Silicon: The First Five Monolayers”, Rodney A. McKee et al., Physical Review Letters, Volume 81, Number 14, Oct. 5, 1998, pp. 3014-3017.
However, these structures have a lattice mismatch that is about 2% off from that of Si. These oxide films are grown on Si surfaces that are oriented in the <100> crystalline direction and while they are aligned in the plane of growth to the spacing of the silicon atoms in the <110> directions in the growth plane to a small level of lattice mismatch, they exhibit a large lattice mismatch to the silicon in the direction perpendicular to the growth plane. Epitaxial structures can also be made with Y2O3 but the lattice mismatch is about 2.5%.
Secondly, such insulators can be used for fully epitaxial Si/insulator/Si epitaxial structures or epitaxial Ge/insulator/Ge epitaxial structures. There have been no prior reports of successful growth of Si/oxide/Si epitaxial structures with a flat interfacial and surface profile for thin (less than about 50 nm) epitaxial layers. These structures can be used for a variety of different applications such as, for example, silicon-on-insulator (SOI) structures or germanium-on-insulator (GOI) structures for transistors, double-gated FET structures, and novel optical and optoelectronic devices.
Thus, prior to the invention, gate dielectrics/insulators have been provided that are epitaxial, but not lattice-matched. However, these dielectrics/insulators are still problematic as lattice mismatch induced defects are created in the devices (e.g., CMOS FET) incorporating such structures. These defects act as traps and affect the turn-on of the device (transistor), as well as the stability and mobility of the device.
In addition, prior to the present invention, no Si substrate/epitaxial oxide/epitaxial silicon structures have been grown that have smooth and uniform surfaces and interfaces for ultrathin layer thicknesses (<50 nm). There has been one report (e.g., see “Epitaxial CeO2 on Silicon Substrates and the Potential of Si/CeO2/si for SOI Structures”, A. H. Morshed et al. Mat. Res. Soc. Symp. V474, 339(1197)) of attempting to grow epitaxial Si films on CeO2 (cerium oxide). However, the Si growth profile was rough and three dimensional and the silicon was not completely epitaxial in nature.
Thus, prior to the present invention, there has not been any lattice-matched epitaxial insulator-silicon structure formed on silicon which is substantially defect-free and uniform, nor has the advantages of such a structure been recognized prior to the present invention. This is also the case for lattice matched epitaxial insulator-germanium structures.